{"id":149,"date":"2022-04-27T07:32:42","date_gmt":"2022-04-27T07:32:42","guid":{"rendered":"http:\/\/eslab.cs.unipi.gr\/?page_id=149"},"modified":"2026-01-20T08:46:08","modified_gmt":"2026-01-20T08:46:08","slug":"projects","status":"publish","type":"page","link":"http:\/\/eslab.cs.unipi.gr\/?page_id=149","title":{"rendered":"Projects"},"content":{"rendered":"\t\t
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NeAIxt: Next Generation of edge AI crossing technology fields

HORIZON-JU-IA<\/h3>

The NeAIxt project is a strategic initiative designed to foster European independence and control over edge AI technology, benefiting both companies and citizens. The project presents a golden opportunity for European SMEs to grow, network, and enhance skills, leveraging exposure to the global market. Research labs and RTOs will bridge the gap to the future by developing necessary technologies and competencies, while universities will cultivate and disseminate advanced skills required for this technological evolution.<\/p>

The ESLab team will participate in the development of an AI platform for real-time natural\/manmade disaster detection and\/ or suspicious
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Representative Test Vehicles for Radiation Tests of Deep Submicron Technologies

ESA<\/h3>

This project will develop and validate a set of methodologies, user guides, benchmarks, and EGSE radiation testing tools to rapidly and accurately estimate the failure rate and failure modes caused by SEEs on UDSM SRAM FPGA-based applications without the need to conduct radiation experiments on every new mission.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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VEMER: Leveraging Voltage Margins and Error Resiliency at Large-Scale Computing

H.F.R.I <\/h3>

VEMER aims to determine how much chip voltage can be reduced while maintaining acceptable Quality of Service (QoS) and dependability metrics for Heterogeneous Computing Platform (HCP) workloads. Specifically, VEMER aims to quantify the Soft Error Rate (SER) of CPUs, GPUs, and FPGAs (ML accelerators) in HCPs under neutron radiation across various undervolting and workload configurations. The findings of this research are expected to have a significant impact on reducing the energy consumption in datacenters.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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Greek Cubesats in-orbit validation

ESA <\/h3>

The ESLab team will develop and validate a Fault Detection, Isolation and Repair (FDIR) Strategy for the FPGA Accelerators of the CubeSat Payloads. It will first estimate the radiation environment specifications of the CubeSat mission and assess the vulnerabilities of the payload FPGA devices against radiation-induced effects. Then, it design and develop FDIR mechanisms (within the area and power budget constraints) for the payload FPGA accelerators and it will perform radiation experiments and\/or fault injection experiments to validate the effectiveness of the FDIR mechanisms<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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Lockstep-SoC: Lockstep-based SEE mitigation approach for COTS SoC FPGAs

ESA, Open Space Innovation Platform (OSIP) <\/h3>

COTS SoC FPGAs provide an attractive platform for building onboard computers due to their advantages in cost, performance, and flexibility, but they suffer from reliability issues caused by radiation-induced phenomena. Our approach aims at providing a computing paradigm that combines the high performance features of the COTS SoC FPGAs with the level of protection provided by radiation-tolerant devices against single event upsets. Particulatly, we will design, implement and validate a loosely-coupled lockstep technique with checkpoint and restore mechanisms for the dual-core Arm-A9 processor of the Xilinx Zynq-7000 APSoC<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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EMNESS: European Master Network on Embedded Systems Security

Horizon EU, Erasmus +<\/h3>

This project is an initiative of an ensemble of European Universities (University of Freiburg, University of Stuttgart, Polytechnic University of Torino, University of Grenoble Alpes, University of Piraeus, Polytechnic University of Catalonia) with the goal to structure innovative academic curriculums on Reliability and Hardware Security, by exchanging expertise on these fields. Prioritizing the use of digital technology, knowledge transfer in an inter-connected and inter-dependent higher education system will be the main objective of this project. The goal will be for the professors to work collectively, address the skill mismatches and cover the knowledge gaps forming a new generation of highly-skilled engineers in Reliability and Hardware Security.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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SecureHLS: EDA tools for Secure and Reliable HLS accelerators

Horizon 2020 - Marie Sk\u0142odowska-Curie Individual Fellowship (PostDoc)<\/h3>

System on Chip (SoC) and Internet of Things (IoT) hardware Hardware attacks, such as Fault Attacks and Side Channel Attacks, are a serious threat for the security of System on Chip (SoC) and Internet of Things (IoT) hardware accelerators. These threats are usually not concurrently addressed since their corresponding protections are not always compatible to each other. In a context, where designers use High Level Synthesis (HLS) flows to increase the productivity of designing hardware accelerators they must also ensure that security and reliability protections are taken into account by the HLS tools. The goal of the project is to provide to SoC and IoT designers, Electronic Design Automation (EDA) tools, capable to evaluate, improve and automate the insertion of protections during an HLS flow.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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ZYNQ-RT: Experimental system for the radiation tests of a Xilinx Zynq-7000 FPGA device

ESA, Lab activity<\/h3>

The project will develop an experimental system for the radiation tests of a Xilinx Zynq-7000 FPGA device. The setup will be based on the Xilinx Zynq-7000 SoC ZC706 evaluation kit and will provide capabilities for accessing the embedded memories of the programmable logic (PL) part (e.g. configuration memory, Block RAM, user Flip-Flops) and the processing system (PS) (e.g. On-chip memory, caches) of the Xilinx Zynq-7000 FPGA in order to facilitate the Single Event Upsets (SEUs) characterization of the device under radiation tests.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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MySpW-FPGA: Myriad 2-SpW interface FPGA-based demonstrator

ESA, Lab activity<\/h3>

The goal of this project is to design and develop an FPGA-based demonstrator for the Myriad 2-SpW interface component to be used as a bridge between the camera interface of the Myriad 2 EOT (Eye of Things) board and a SpW link. The Myriad 2-SpW interface design will be ported into a Xilinx UltraScale FPGA (XCKU040) device embedded on a Xilinx Kintex UltraScale Development Kit. The system will be demonstrated in-field in heavy-ion (in CERN and GSI accelerators) and proton (in PSI facility) radiation experiments.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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SYSYFOS: Development of an integrated system for high-performance and high-reliability compressions and management of hyperspectral image data

GSRT (Research-Create-Innovate) <\/h3>

The project will develop a state-of-the-art hardware accelerator for lossy compression of hyperspectral images with high fidelity at high compression ratios based on the upcoming CCSDS 122.1-B-1 standard and a modified CCSDS 122.0-B-2 standard. The hardware accelerator will be integrated in a single SRAM FPGA SoC along with the industry standard onboard network protocols (SpaceWire). The ESLab team will develop a novel Fault Detection, Isolation and repair (FDIR) strategy targeting Single Event Effects (SEEs) for the hardware accelerator at IP core level, as well as, at SoC level providing a novel low-cost, low-power, fault tolerant version of the hardware accelerator.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t

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MELITY: Development of Methodologies and Embedded Security Solutions for e-health services based on Internet of Things technologies

GSRT (Research-Create-Innovate)<\/h3>

The objective of this project is the development of innovative methodologies and embedded security solutions for the protection of Internet-of-Medical-Things (IoMT) technologies used in realtime e-health services. The ESLab will deal with the vulnerability analysis of the \u0399\u03bf\u039c\u03a4 devices agaings side-channel (power and EM) attacks \u03ba\u03b1\u03b9 fault injection attacks and the design of relative countermeasures.<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/a>\t\t\t\t<\/div>\n\n\t\t\t<\/div>\n\t\t\t\t\t\t<\/section>\n\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Embedded Systems Laboratory<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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eslab@unipi.gr<\/span><\/p>\n


<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

Projects Projects 2025 – 2028 2025 – 2028 NeAIxt: Next Generation of edge AI crossing technology fields HORIZON-JU-IA The NeAIxt project is a strategic initiative designed to foster European independence and control over edge AI technology, benefiting both companies and citizens. The project presents a golden opportunity for European SMEs to grow, network, and enhance… Read More »Projects<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"page-templates\/template-pagebuilder-full-width.php","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"","neve_meta_content_width":0,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":"","footnotes":""},"class_list":["post-149","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages\/149","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=149"}],"version-history":[{"count":84,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages\/149\/revisions"}],"predecessor-version":[{"id":945,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages\/149\/revisions\/945"}],"wp:attachment":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=149"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}