{"id":8,"date":"2022-04-26T20:03:35","date_gmt":"2022-04-26T20:03:35","guid":{"rendered":"http:\/\/eslab.cs.unipi.gr\/?page_id=8"},"modified":"2023-10-18T20:06:35","modified_gmt":"2023-10-18T20:06:35","slug":"home-2","status":"publish","type":"page","link":"http:\/\/eslab.cs.unipi.gr\/","title":{"rendered":"Home"},"content":{"rendered":"\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t\t
<\/div>\n\t\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t
<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t

ESLAB<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t

Embedded Systems Laboratory<\/p>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t

ESLab<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t

The Embedded Systems Lab (ESLab) is specialized in\u00a0 the design of Dependable Embedded Systems, particularly in the development of hardware and software-based methodologies for the testing, reliability, and security of embedded systems with emphasis on embedded processors and Field Programmable Gate Arrays (FPGAs).<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\"\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\"UNIPI_logo\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
\n\t\t\t\t\t\t\t
<\/div>\n\t\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t

Research topics<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t
\"\"<\/figure>

Field Programmable Gate Arrays (FPGA) Reliability <\/h3>

  • Radiation effects analysis in COTS FPGAs <\/li>\n
  • Single Event Effect (SEE) characterization of COTS FPGAs with radiation and fault injection experiments<\/li> \n
  • Reliability analysis of FPGA accelerators (deep neural networks, image compressors, approximate circuits) <\/li>\n
  • Single Event Effect (SEE) mitigation approaches<\/li>\n
  • Fault Detection, Isolation and Repair (FDIR) methodologies for FPGAs<\/li><\/p><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t
    \"\"<\/figure>

    Microprocessor Reliability<\/h3>

  • Functional testing methodologies for embedded processors,\nmulticore processors and SoCs\n
  • Reliability analysis of microprocessors with radiation and fault injection experiments\n
  • Fault-tolerant processors for critical applications\n<\/p><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t
    \"\"<\/figure>

    Hardware Security <\/h3>

  • Security analysis and countermeasure design for FPGAs, embedded systems and ICs \n
  • Side-Channel & Fault-Injection attacks\n
  • EDA tools for Hardware Security\n
  • Physically Unclonable Functions (PUF)<\/p><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
    \n\t\t\t\t\t\t\t
    <\/div>\n\t\t\t\t\t\t\t
    \n\t\t\t\t\t
    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t

    news<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t\t
    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t\t\t
    \n\t\t\t\t\t\t\t
    \n\t\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t01\/09\/2023-\u0395\u03bd\u03ad\u03c1\u03b3\u03b5\u03b9\u03b5\u03c2 \u0394\u03b7\u03bc\u03bf\u03c3\u03b9\u03cc\u03c4\u03b7\u03c4\u03b1\u03c2 - \u0395\u03c0\u03b9\u03c7\u03b5\u03b9\u03c1\u03b7\u03c3\u03b9\u03b1\u03ba\u03cc \u03c0\u03c1\u03cc\u03b3\u03c1\u03b1\u03bc\u03bc\u03b1 \u0391\u03c4\u03c4\u03b9\u03ba\u03ae 2014-2020<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

    \u03a4\u03bf \u03b5\u03c1\u03b3\u03b1\u03c3\u03c4\u03ae\u03c1\u03b9\u03bf \u03c7\u03c1\u03b7\u03c3\u03b9\u03bc\u03bf\u03c0\u03bf\u03b9\u03b5\u03af \u03b5\u03be\u03bf\u03c0\u03bb\u03b9\u03c3\u03bc\u03cc \u03c4\u03bf\u03c5 \u03b5\u03c1\u03b3\u03b1\u03c3\u03c4\u03b7\u03c1\u03af\u03bf\u03c5 \u0391\u03c3\u03c6\u03ac\u03bb\u03b5\u03b9\u03b1\u03c2, \u03c0\u03bf\u03c5 \u03ad\u03c7\u03b5\u03b9 \u03c7\u03c1\u03b7\u03bc\u03b1\u03c4\u03bf\u03b4\u03bf\u03c4\u03b7\u03b8\u03b5\u03af \u03b1\u03c0\u03cc \u03c4\u03b7\u03bd \u03a0\u03b5\u03c1\u03b9\u03c6\u03ad\u03c1\u03b5\u03b9\u03b1 \u0391\u03c4\u03c4\u03b9\u03ba\u03ae\u03c2, \u03b3\u03b9\u03b1 \u03c4\u03b7\u03bd \u03b1\u03bd\u03ac\u03c0\u03c4\u03c5\u03be\u03b7 \u03ba\u03b1\u03c4\u03b1\u03bd\u03b5\u03bc\u03b7\u03bc\u03ad\u03bd\u03c9\u03bd \u03c5\u03c0\u03b7\u03c1\u03b5\u03c3\u03b9\u03ce\u03bd blockchain \u03c0\u03bf\u03bb\u03bb\u03b1\u03c0\u03bb\u03ce\u03bd \u03ba\u03cc\u03bc\u03b2\u03c9\u03bd. \u0397 \u03c5\u03c0\u03bf\u03b4\u03bf\u03bc\u03ae \u03b8\u03b1 \u03c7\u03c1\u03b7\u03c3\u03b9\u03bc\u03bf\u03c0\u03bf\u03b9\u03b7\u03b8\u03b5\u03af \u03b3\u03b9\u03b1 \u03b5\u03c1\u03b5\u03c5\u03bd\u03b7\u03c4\u03b9\u03ba\u03bf\u03cd\u03c2 \u03ba\u03b1\u03b9 \u03b1\u03bd\u03b1\u03c0\u03c4\u03c5\u03be\u03b9\u03b1\u03ba\u03bf\u03cd\u03c2 \u03c3\u03ba\u03bf\u03c0\u03bf\u03cd\u03c2, \u03c3\u03b5 \u03c3\u03c5\u03bd\u03b5\u03c1\u03b3\u03b1\u03c3\u03af\u03b1 \u03bc\u03b5 \u03b5\u03bd\u03b4\u03b9\u03b1\u03c6\u03b5\u03c1\u03cc\u03bc\u03b5\u03bd\u03bf\u03c5\u03c2 \u03bf\u03c1\u03b3\u03b1\u03bd\u03b9\u03c3\u03bc\u03bf\u03cd\u03c2 \u03c4\u03bf\u03c5 \u03b4\u03b7\u03bc\u03cc\u03c3\u03b9\u03bf\u03c5 \u03ba\u03b1\u03b9 \u03c4\u03bf\u03c5 \u03b9\u03b4\u03b9\u03c9\u03c4\u03b9\u03ba\u03bf\u03cd \u03c4\u03bf\u03bc\u03ad\u03b1.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

    \n\t\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t19\/03\/2023-Our new work entitled \"Single Event Effects Assessment of UltraScale+ MPSoC Systems under Atmospheric Radiation\"<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

    \"\"AMD incorporates soft error mitigation mechanisms in its UltraScale+ MPSoC devices to recover memory upsets (i.e., faults) before they propagate to the application output and become an error.<\/p>

    But how effective are these soft error mitigation mechanisms? Can they effectively recover upsets in high altitude or large scale applications under different workloads?<\/p>

    Our new work entitled “Single Event Effects Assessment of UltraScale+ MPSoC Systems under Atmospheric Radiation”
    (https:\/\/lnkd.in\/dQjqfDWg) answers the above research questions through a solid study that entails accelerated neutron radiation testing and dependability analysis.<\/p>

    We test the device on a broad range of workloads, like multi-threaded software used for pose estimation and weather prediction or a software\/hardware (SW\/HW) codesign image classification application running on the AMD Deep Learning Processing Unit (DPU)<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

    \n\t\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t16\/03\/2023-Thanks to everyone that attended our poster presentation at SEFUW: SpacE FPGA Users Workshop, 5th Edition at ESA\/ESTEC.<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

    \"\"<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

    \n\t\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t04\/03\/2023-Our new Hardware Security platform capable of performing precise EM-based Side Channel and Fault Injection evaluations is up and running<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

    \"\"<\/p>

    \u0397 \u03c5\u03c0\u03bf\u03b4\u03bf\u03bc\u03ae \u03ad\u03c7\u03b5\u03b9 \u03c7\u03c1\u03b7\u03bc\u03b1\u03c4\u03bf\u03b4\u03bf\u03c4\u03b7\u03b8\u03b5\u03af \u03b1\u03c0\u03cc \u03c4\u03b7\u03bd \u03a0\u03b5\u03c1\u03b9\u03c6\u03ad\u03c1\u03b5\u03b9\u03b1 \u0391\u03c4\u03c4\u03b9\u03ba\u03ae\u03c2 \u03c3\u03c4\u03b1 \u03c0\u03bb\u03b1\u03af\u03c3\u03b9\u03b1 \u03c4\u03bf\u03c5 \u03b5\u03c0\u03b9\u03c7\u03b5\u03b9\u03c1\u03b7\u03c3\u03b9\u03b1\u03ba\u03bf\u03cd \u03c0\u03c1\u03bf\u03b3\u03c1\u03ac\u03bc\u03bc\u03b1\u03c4\u03bf\u03c2 \u00ab\u0391\u03a4\u03a4\u0399\u039a\u0397\u00bb \u0386\u03be\u03bf\u03bd\u03b1\u03c2 \u03a0\u03c1\u03bf\u03c4\u03b5\u03c1\u03b1\u03b9\u03cc\u03c4\u03b7\u03c4\u03b1\u03c2: 01 \u00ab\u0395\u03bd\u03af\u03c3\u03c7\u03c5\u03c3\u03b7 \u03c4\u03c9\u03bd \u039c\u03b7\u03c7\u03b1\u03bd\u03b9\u03c3\u03bc\u03ce\u03bd \u03ba\u03b1\u03b9 \u03c4\u03c9\u03bd \u0395\u03c0\u03b5\u03bd\u03b4\u03cd\u03c3\u03b5\u03c9\u03bd \u03c4\u03c9\u03bd \u039c\u039c\u0395 \u03c4\u03b7\u03c2 \u03a0\u03b5\u03c1\u03b9\u03c6\u03ad\u03c1\u03b5\u03b9\u03b1\u03c2 \u0391\u03c4\u03c4\u03b9\u03ba\u03ae\u03c2 \u03c3\u03c4\u03b7\u03bd \u0388\u03c1\u03b5\u03c5\u03bd\u03b1 \u03ba\u03b1\u03b9 \u03c4\u03b7\u03bd \u039a\u03b1\u03b9\u03bd\u03bf\u03c4\u03bf\u03bc\u03af\u03b1\u00bb \u03bf \u03bf\u03c0\u03bf\u03af\u03bf\u03c2 \u03c3\u03c5\u03b3\u03c7\u03c1\u03b7\u03bc\u03b1\u03c4\u03bf\u03b4\u03bf\u03c4\u03b5\u03af\u03c4\u03b1\u03b9 \u03b1\u03c0\u03cc \u03c4\u03bf \u0395\u03c5\u03c1\u03c9\u03c0\u03b1\u03ca\u03ba\u03cc \u03a4\u03b1\u03bc\u03b5\u03af\u03bf \u03a0\u03b5\u03c1\u03b9\u03c6\u03b5\u03c1\u03b5\u03b9\u03b1\u03ba\u03ae\u03c2 \u0391\u03bd\u03ac\u03c0\u03c4\u03c5\u03be\u03b7\u03c2 (\u0395\u03a4\u03a0\u0391) \u03bc\u03b5 \u03c4\u03af\u03c4\u03bb\u03bf \u00ab\u0391\u03bd\u03ac\u03c0\u03c4\u03c5\u03be\u03b7 \u03a5\u03c0\u03bf\u03b4\u03bf\u03bc\u03ce\u03bd \u03ba\u03b1\u03b9 \u0394\u03bf\u03bc\u03ce\u03bd \u03c3\u03b5 \u03ba\u03c1\u03af\u03c3\u03b9\u03bc\u03b5\u03c2 \u03c0\u03b5\u03c1\u03b9\u03bf\u03c7\u03ad\u03c2 \u03ba\u03b1\u03b9 \u03c4\u03bf\u03bc\u03b5\u03af\u03c2 \u0395&\u039a \u03c3\u03b5 \u03c3\u03c5\u03bc\u03c6\u03c9\u03bd\u03af\u03b1 \u03bc\u03b5 \u03c4\u03b7\u03bd \u03a5\u03bb\u03bf\u03c0\u03bf\u03af\u03b7\u03c3\u03b7 \u03c4\u03b7\u03c2 RIS3 \u03c4\u03b7\u03c2 \u03a0\u03b5\u03c1\u03b9\u03c6\u03ad\u03c1\u03b5\u03b9\u03b1\u03c2 \u0391\u03c4\u03c4\u03b9\u03ba\u03ae\u03c2\u00bb.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

    \n\t\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t24\/10\/2022-Our work \u201cA Methodology for Fault-Tolerant Pareto-Optimal Approximate Designs of FPGA-based Accelerators\u201d just got accepted to the ACM Transactions on Embedded Computing Systems.<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

    Approximate Computing Techniques (ACTs) are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency.
    However, an important question comes to mind when targeting critical systems; Does ACT optimisation negatively affect the reliability of the system, and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy (TMR) with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability?

    Our work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation and hardware redundancy in the design. \"\"<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

    \n\t\t\t\t
    \n\t\t\t\t\t\t\t
    \n\t\t\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t\tLinkedin-in<\/span>\n\t\t\t\t\t\t<\/i>\t\t\t\t\t<\/a>\n\t\t\t\t<\/span>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t\t
    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\"\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t\t\t
    \n\t\t\t\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t

    Embedded Systems Laboratory<\/p>

    \u00a0<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

    \n\t\t\t
    \n\t\t\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t\t\t
    \n\t\t\t\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
    \n\t\t\t\t
    \n\t\t\t\t\t\t\t\t\t

    eslab@unipi.gr<\/span><\/p>\n


    <\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

    ESLAB Embedded Systems Laboratory ESLab The Embedded Systems Lab (ESLab) is specialized in\u00a0 the design of Dependable Embedded Systems, particularly in the development of hardware and software-based methodologies for the testing, reliability, and security of embedded systems with emphasis on embedded processors and Field Programmable Gate Arrays (FPGAs). Research topics Field Programmable Gate Arrays (FPGA)… Read More »Home<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"page-templates\/template-pagebuilder-full-width.php","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"","neve_meta_content_width":0,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":"","footnotes":""},"class_list":["post-8","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages\/8","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=8"}],"version-history":[{"count":116,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages\/8\/revisions"}],"predecessor-version":[{"id":931,"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=\/wp\/v2\/pages\/8\/revisions\/931"}],"wp:attachment":[{"href":"http:\/\/eslab.cs.unipi.gr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=8"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}