VEMER

Leveraging Voltage Margins and Error Resiliency at Large-Scale Computing

Consortium

    • University of Piraeus (Unipi) – Embedded Systems Laboratory (ESLab)

    • National and Kapodistrian University of Athens (NKUA) – Computer Architecture Laboratory (CAL)

Goals

The project aims to: 

  • Study the impact of voltage underscaling on the occurrence of radiation-induced soft errors for various processors and hardware accelerators employed in today’s data centers by performing neutron radiation experiments

  • Leverage the voltage margins of these chips and the error resiliency of ML applications in order to maximize the energy savings at large-scale subject to a minimum computation accuracy loss and reliability degradation.

Publications

    • D. Agiakatsikas, G. Papadimitriou, V. Karakostas, D. Gizopoulos, M. Psarakis and C. Bélanger-Champagne, “Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs,” 2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO), Toronto, ON, Canada, 2023, pp. 957-971.

    • L. Yang, G. Papadimitriou, D. Sartzetakis, A. Jog, E. Smirni and D. Gizopoulos, “Probing Weaknesses in GPU Reliability Assessment: A Cross-Layer Approach,” 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Indianapolis, IN, USA, 2024, pp. 331-333, doi: 10.1109/ISPASS61541.2024.00048.

    • O. Chatzopoulos, M. Trakosa, G. Papadimitriou, W. S. Wong and D. Gizopoulos, “SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs,” 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Indianapolis, IN, USA, 2024, pp. 120-131, doi: 10.1109/ISPASS61541.2024.00021.

    • Ioanna Souvatzoglou, Konstantinos Argyriou, Grigoris Karaoglanian, Dimitris Agiakatsikas, Mihalis Psarakis, Investigating Undervolting Effects on RISC-V Implemented in FPGA, RESCUER: (REliable and SeCUrE RISC-V architectures) Workshop; held in conjunction with the European Test Symposium (ETS), May 2025.

    • M. Trakosa, O. Chatzopoulos, G. Papadimitriou and D. Gizopoulos, “NAVIgator: Exploring the Voltage Limits of AMD NAVI GPUs for Energy Efficient Computing,” 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS), Ischia, Italy, 2025, pp. 1-8, doi: 10.1109/IOLTS65288.2025.11117086.

    • Konstantinos Argyriou, Grigoris Karaoglanian, Dimitris Agiakatsikas, Mihalis Psarakis, “Voltage Scaling for Energy-Efficient and Reliable FPGA Deep Neural Network Acceleration,”20th International Conference on Design, Test & Technology of Integrated Systems (DTTIS), Athens, Greece, Oct. 2025.

    • Ioanna Souvatzoglou, Konstantinos Argyriou, Grigoris Karaoglanian, Dimitris Agiakatsikas and Mihalis Psarakis, “Power-Efficient FPGA Acceleration of Quantized Neural Networks through Safe Undervolting,”, International Conference on Field Programmable Technology (FPT), Shanghai, China, Dec. 2025.

    • Ioanna Souvatzoglou, Konstantinos Argyriou, Grigoris Karaoglanian, Dimitris Agiakatsikas, Mihalis Psarakis, Maria Kastriotou, and Carlo Cazzaniga, “A Joint Evaluation of FPGA QNN Accelerators under Voltage Scaling and Neutron-Induced Faults”, IEEE Transactions on Nuclear Science, under review.

    • George Papadimitriou, Dimitris Agiakatsikas, Konstantinos Argyriou, Dimitris Gizopoulos, Mihalis Psarakis, and Maria Kastriotou, “Evaluating Soft Error Vulnerability and Process Variation in Multicore CPUs Under Voltage Scaling”, IEEE Transactions on Computers, under review.